Exploring the RISC-V processor architecture

The open source RISC-V processor architecture is poised to shake up the processor industry. Thanks to the Qemu emulator, you can get to know the RISC-V without waiting for affordable hardware.

Most of the IT industry has consolidated around Intel-equivalent processors with the x86 and (related) AMD64 architectures. But just two decades ago, several other processor manufacturers and architectures were fighting for a place in the market. Many of these processors (including MIPS, PowerPC, Alpha, and SPARC) followed a set of principles for processor design known as Reduced Instruction Set Computer (RISC). RISC systems live on today, most notably in the ARM architecture used in today’s in smartphones, Raspberry Pis, and other electronic devices. (The acronym ARM actually stands for Advanced RISC Machine.) But another RISC contender is also on the rise.

RISC-V, pronounced “Risk Five,” is widely hailed as a shooting star in the processor architecture sky [1]. Proponents believe RISC-V can do everything ARM can do – and it is all open source and royalty free. The non-proprietary nature of RISC-V means it could allow small chip makers to get in a game that is now dominated by a few tech giants. And even mainstream vendors could one day gain an edge by choosing RISC-V and avoiding licensing fees.

At just 10 years old, the RISC-V architecture is still considered comparatively young. If you can live without Linux and prefer FreeRTOS, you can get started today and gain some RISC-V experience on reasonably priced hardware (see the box entitled “Hardware Options”). Until recently, if you were looking for a RISC-V processor capable of running Linux, you would have to pay as much as EUR600. As this issue goes to print, an affordable, Linux-ready RISC-V board has finally reached the market, though little is known about it [2].

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